Ponde mult18_dividers

9 x 9 multipliers (in addition to 18 x 18 multipliers) are available in the Altera FPGA architecture.
Using a 9 x 9 multiplier, a 1/256 divider or a 1/128 divider can be constructed.

1/2^8 divider

delta=3 produces 256 unique mult18_d values and there are five values with bit-15 being high:
0x80f4 (12)
0x81fa (46)
0x8071 (47)
0x8177 (69)
0x827d (139) // «—-

The lower 8-bit of mult18_d is unique. The lower 8-bit can be used for pseudo random generation.

// this acts as 1/256 divider (8-bit)
assign flip2blink_d =
    &{mult18_d[15], mult18_d[9], blnkFs_d};

MULT9X9S i_mult (
    .P (mult18_d),
    .A ({1'b0, mult18_d[8-1:1], ~mult18_d[0]}),
    .B (coef9_d),
    .C (sysclk),
    .CE (blnkFs_d),
    .R (sysrst)
    );

// 0.5 + a (where a << 0.5)
assign coef9_d =
    9'h080 + 9'd3;

1/2^7 divider

delta=3 produces 128 unique mult18_d values and there are two values with bit-14 being high, 0x40fd (11) and 0x407a (46).

// this acts as 1/128 divider (7-bit)
assign flip2blink_d =
    &{mult18_d[14], mult18_d[7], blnkFs_d};

MULT9X9S i_mult (
    .P (mult18_d),
    .A ({1'b0, mult18_d[7-1:1], ~mult18_d[0]}),
    .B (coef9_d),
    .C (sysclk),
    .CE (blnkFs_d),
    .R (sysrst)
    );

// 0.5 + a (where a << 0.5)
assign coef9_d =
    9'h080 + 9'd3;

Synthesizable MULT9X9S

`timescale  1 ns / 1 ps

module MULT9X9S (P, A, B, C, CE, R);

    output [17:0] P;

    input  [8:0] A;
    input  [8:0] B;
    input  C, CE, R;

    tri0 GSR = glbl.GSR;

    reg [18-1:0]    p_out;
    wire [18-1:0]   A_, B_, p_in;

    assign P = p_out;

    assign A_ = { {9{A[8]}}, A };
    assign B_ = { {9{B[8]}}, B };

    assign p_in = A_ * B_;

    always @(posedge C or posedge GSR)
     if (GSR)
        p_out = {18{1'b0}};
     else
        if (R)
            p_out <= {18{1'b0}};
        else if (CE)
            p_out <= #1 p_in;

endmodule
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