Ponde mult36_dividers

18 x 18 multipliers (in addition to 9 x 9 multipliers) are available in the Altera FPGA architecture.
Using a 18 x 18 multiplier, a 1/2^17 divider or a 1/12^16 divider or a 1/2^15 divider can be constructed.

1/2^17 divider

delta=3 produces 131072 (2^17) values and there are five values with bit-33 being high:
0x20001fff4, 15628
0x20003fffa, 66734
0x20000fff1, 66735
0x20004fffd, 81163 // «<—-
0x20002fff7, 92741

// this acts as 1/131072 divider (17-bit)
assign flip2blink_d =
    &{mult36_d[33], mult36_d[18], blnkFs_d};

MULT18X18S i_mult (
    .P (mult36_d),
    .A ({1'b0, mult36_d[17-1:1], ~mult36_d[0]}),
    .B (coef18_d),
    .C (sysclk),
    .CE (blnkFs_d),
    .R (sysrst)
    );

// 1.0 + a (where a << 1.0)
assign coef18_d =
    18'h10000 + 18'd3;

1/2^16 divider

delta=3 produces 65536 (2^16) unique values and there are two values with bit-32 being high, 0x10000fffa (1198) and 0x10001fffd (15627).

// this acts as 1/65536 divider (16-bit)
assign flip2blink_d =
    &{mult36_d[32], mult36_d[16], blnkFs_d};

MULT18X18S i_mult (
    .P (mult36_d),
    .A ({2'b00, mult36_d[16-1:1], ~mult36_d[0]}),
    .B (coef18_d),
    .C (sysclk),
    .CE (blnkFs_d),
    .R (sysrst)
    );

// 1.0 + a (where a << 1.0)
assign coef18_d =
    18'h10000 + 18'd3;

1/2^15

delta=3 produces 32768 (2^15) unique values and there is only one value with bit-31 being high, 0x80007ffd (15627).

// this acts as 1/32768 divider (15-bit)
assign flip2blink_d =
    &{mult36_d[31], blnkFs_d};

MULT18X18S i_mult (
    .P (mult36_d),
    .A ({3'b000, mult36_d[15-1:1], ~mult36_d[0]}),
    .B (coef18_d),
    .C (sysclk),
    .CE (blnkFs_d),
    .R (sysrst)
    );

// 1.0 + a (where a << 1.0)
assign coef18_d =
    18'h10000 + 18'd3;

Synthesizable MULT18X18S

`timescale  1 ns / 1 ps

module MULT18X18S (P, A, B, C, CE, R);

    output [35:0] P;

    input  [17:0] A;
    input  [17:0] B;
    input  C, CE, R;

    tri0 GSR = glbl.GSR;

    reg [36-1:0]    p_out;
    wire [36-1:0]   A_, B_, p_in;

    assign P = p_out;

    assign A_ = { {18{A[17]}}, A };
    assign B_ = { {18{B[17]}}, B };

    assign p_in = A_ * B_;

    always @(posedge C or posedge GSR)
     if (GSR)
        p_out = {36{1'b0}};
     else
        if (R)
            p_out <= {36{1'b0}};
        else if (CE)
            p_out <= #1 p_in;

endmodule
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